1. Technical Field
The present invention relates to a test apparatus. More particularly, the present invention relates to a test apparatus that tests a device under test, such as a semiconductor circuit, with different test periods.
2. Related Art
Testing a device under test, such as a semiconductor circuit, with different test periods involves inputting a prescribed test pattern to each pin of the device under test and judging whether the device under test is operating correctly. The test pattern may be a pattern signal that includes a prescribed data pattern, a clock signal having a prescribed period, or a control signal that operates the device under test.
Each test pattern is generated by a corresponding test module of the test apparatus. For example, each test module may generate a test pattern having a prescribed pattern by performing a preset test sequence with a test period corresponding to the test pattern to be generated. More specifically, each test module may generate a test pattern having a prescribed logic pattern by outputting a plurality of supplied logic patterns in an order designated by the test sequence. When each test pattern has a different period, the test period at which each test module operates may be different as well (e.g. International Publication Pamphlet No. 2003/062843 and Japanese Patent Application Publication No. 11-14714).
It is desirable that the test patterns be input in synchronization to the pins of the device under test. One way of achieving this is by synchronizing the timings at which each test module begins to supply the test pattern to the device under test (e.g. International Publication Pamphlet No. 2003/062843).
The test modules sequentially generate the logic patterns according to the test sequence. The test modules sequentially transmit these logic patterns to the device under test through pipelines operating in accordance with the test period. In other words, by controlling the timing at which the signal begins to be output from the final circuit of each pipeline, the timings at which each test module begins to supply the test pattern to the device under test can be synchronized. More specifically, a logic pattern corresponding to the number of stages of each pipeline is generated and stored in the corresponding pipeline, and a test pattern begins to be output from the last circuit of each pipeline at substantially the same time. By performing such an operation, a plurality of test modules having different test periods can begin to supply each test pattern in synchronization.
The referenced Patent Documents include International Publication Pamphlet No. 2003/062843 and Japanese Patent Application Publication No. 11-14714.
The test sequence performed by each test module may includes a repeat instruction that creates a loop during testing until a prescribed condition is fulfilled. For example, each test module may repeatedly generate a constant logic pattern until the test apparatus, the device under test, and the like fulfills the prescribed condition during testing. When the prescribed condition is fulfilled, each test module may output the logic pattern corresponding to the subsequent test sequence.
In this case as well, it is desirable to synchronize the timings at which each test module supplies the logic pattern corresponding to the subsequent test sequence to the device under test. However, even when the timing at which each test module performs the subsequent test sequence is synchronized, the timing at which the subsequent logic pattern is output from the final stage of each pipeline may be out of synchronization due to a difference in the number of stages in the pipeline and the test period of each test module.
While the repeat instruction is being performed, the logic pattern used to create the loop is stored in the pipeline. Therefore, the logic pattern corresponding to the subsequent test sequence after exiting the loop cannot be stored in the pipeline in advance, so that the logic patterns after exiting the loop cannot be output in synchronization, even if the timing of the output of the final circuit in each pipeline is controlled to begin outputting the test pattern at the same time as described above.